The present invention generally relates to a signal processing circuit, and, more particularly, to a signal processing circuit for preventing the pseudo lock of a timing recovery PLL which generates a clock signal having a phase that is substantially coincident with the phase of a recording medium read signal.
FIG. 1 is a schematic block diagram of a conventional signal processing circuit 10. The signal processing circuit 10 includes an analog-to-digital converter (ADC) 11, a decision feedback equalizer (DFE) 12, coefficient registers 13 and 14, a PLL phase error detection circuit 15, a timing recovery PLL (TR-PLL) 16, and a control circuit 17.
The ADC 11 samples an analog signal read from a recording medium in accordance with a clock signal CLK supplied from the TR-PLL 16 and converts the analog read signal to a digital read signal. The DFE 12 includes a forward (FW) filter 21, an adder 22, a comparator 23, a shift register 24, a feedback (FB) filter 25, an inverter circuit 26, and switches 27, 28, and 29.
The first and second coefficient registers 13 and 14 are connected to the FW filter 21 via the first switch 27. The first coefficient register 13 prestores a first filter coefficient (start value) used by the FW filter 21 at startup (i.e., initial read operation). The second coefficient register 14 prestores a second filter coefficient (normal value) used by the FW filter 21 during normal operation (after preamble data has been detected). At startup, the FW filter 21 receives the digital read signal supplied from the ADC 11 and the first filter coefficient via the first switch 27 and filters the digital read signal using the first filter coefficient so that the S/N (signal-to-noise) ratio is maximized. During normal operation, the FW filter 21 filters the digital read signal using the second filter coefficient.
The adder 22 receives the filtered digital read signal S1 from the FW filter 21 and a feedback signal S2 supplied from the FB filter 25 via the third switch 29 and adds the filtered digital read signal S1 and an inverse signal of the feedback signal S2. That is, the adder 22 functions as a subtractor that subtracts the feedback signal S2 from the filtered digital read signal S1.
The comparator 23 compares the voltage of an operation result signal S3 from the adder 22 and a reference voltage REF and generates a decision signal S4 of “1” or “0”. The shift register 24 receives the decision signal S4 supplied from the comparator 23 via the second switch 28 and samples the decision signal S4 in accordance with the clock signal CLK. Thus, the shift register 24 stores sampling data (i.e., plural pieces of sampled bit data).
The data (decision signal S4) stored in the first-bit register of the shift register 24 is output from the shift register 24 as a reproduction data signal. In this manner, the DFE 12 reproduces the data recorded on the recording medium.
The FB filter 25 receives the sampling data from the shift register 24, eliminates inter-code interference contained in the sampling data, and generates the feedback signal S2.
The PLL phase error detection circuit (hereinafter referred as detection circuit) 15 receives the operation result signal S3 from the adder 22 and a signal S6 (the decision signal S4 from the comparator 23 or an output signal S5 of the inverter circuit 26), detects an error between the phase of the read signal and the phase of the clock signal CLK using the signals S3 and S6, and supplies a control signal S7 to the TR-PLL 16.
The TR-PLL 16 receives the control signal S7 from the detection circuit 15 and generates the clock signal CLK that is substantially coincident with the phase of the read signal in accordance with the control signal S7. Thus, the shift register 24 samples the decision signal S4 of the comparator 23 in accordance with the clock signal CLK (the bit transfer rate of the read signal RD).
The control circuit 17 controls each of the switches 27 to 29 based on the status of the data signal output from the shift register 24 and the number of bytes read from the start of the read operation. Predetermined preamble data is recorded on the recording medium. The preamble data is pattern data in which a predetermined bit is repeated continuously. Accordingly, the control circuit 17 controls each of the switches 27 to 29 in accordance with a predetermined timing based on the number of bytes of the preamble data. Specifically, the control circuit 17 controls each of the switches 27 to 29 as described below.
(1) When the read operation is started, the control circuit 17 switches the first switch 27 to the input of the first coefficient register 13, the second switch 28 to the output of the comparator 23, and the third switch 29 to OPEN. The FW filter 21 waveform-shapes the digital read signal from the ADC 11 using the first filter coefficient (start value) from the first coefficient register 13. The adder 22 supplies the filtered digital signal S1 from the FW filter 21 to the comparator 23. The detection circuit 15 supplies the control signal S4 to the TR-PLL 16 using the filtered digital read signal S1 and the decision signal S4. Accordingly, the TR-PLL 16 performs phase matching of the clock signal CLK using the read signal.
(2) When the bit string (“+++” or “−−−” in this case) of the preamble data is supplied from the shift register 24 to the control circuit 17 a predetermined number of times (for example, three times), the control circuit 17 switches the first switch 27 to the input of the second coefficient register 14, the second switch 28 to the output of the inverter circuit 26, and the third switch 29 to CLOSED. “+” indicates that the voltage of the sampled read signal RD is higher than the reference voltage REF, and “−” indicates the reverse.
The FW filter 21 waveform-shapes the digital read signal from the ADC 11 using the second filter coefficient (normal value) from the second coefficient register 14. The shift register 24 receives the sampling data of the shift register 24 inverted by the inverter circuit 26 via the second switch 28. Accordingly, the shift register 24 repeatedly stores the bit string “+++−−−” of the preamble data. Consequently, the data stored in the shift register is initialized as the preamble data.
The adder 22 receives the filtered digital read signal S1 supplied from the FW filter 21 and the feedback signal S2 supplied from the FB filter 25 via the third switch 29 and adds the filtered digital read signal S1 and the feedback signal S2.
(3) The control circuit 17 counts the number of data pieces supplied from the shift register 24 after the control of the aforementioned (2) and enables frequency matching of the TR-PLL 16 after a predetermined number of data pieces (for example, five bytes) are counted.
(4) The control circuit 17 counts the number of data pieces supplied from the shift register 24 after the control of the aforementioned (3) and switches (maintains) the first switch 27 to the input of the second coefficient register 14, the second switch 28 to the output of the comparator 23, and the third switch 29 to CLOSED. Thus, the TR-PLL 16 performs the phase matching of the clock signal CLK and the DFE 12 outputs a reproduction signal in accordance with the clock signal CLK.
However, high speed information reading of recording medium (or the high density of the recording medium) shortens the read period of the preamble data and the phase matching time of the TR-PLL 16. In other words, the setting change of the FW filter 21, the on/off control of the feedback loop, the preamble synchronization of the shift register 24, and the time for initializing the feedback loop by the control circuit 17 are shortened. As a result, the control timing for each of the switches 27 to 29 using the control circuit 17 becomes inaccurate, and the phase matching of the TR-PLL 16 is not performed accurately. Accordingly, valid read data is not obtained.
The control circuit 17 determines the control timing for each of the switches 27 to 29 based on the number of preamble data pieces. That is, the control circuit 17 does not perform the timing control until the predetermined number of data pieces is supplied even if the phase of the clock signal CLK and the phase of the read signal are substantially coincident at an early stage. This prolongs the phase matching time of the TR-PLL 16.
Further, phase control advances or delays the phase of the clock signal CLK. If the feedback loop is closed (i.e., the third switch 29 is closed) when phase matching of the clock signal CLK is not completed, the TR-PLL 16 may fall into a pseudo lock condition. Specifically, when the phase matching is not complete, the feedback signal S2 having a higher value than the desired value is supplied to the adder 22. In this case, the decision result of the preamble data by the comparator 23 ends in a result (for example, “++−−−−”) that is different from the original decision result. In the decision result, the amount of control for advancing and delaying the phase substantially become equal. As a result, the TR-PLL16 generates a stable clock signal CLK at a frequency shifted from the frequency of the read signal RD. When the TR-PLL 16 is pseudo-locked, it is necessary to resume the read operation, which delays the read speed. One way to prevent the pseudo lock is to increase the number of preamble data pieces. However, increasing the number of preamble data pieces hinders high-density recording on the recording medium and high-speed reading.
It is an object of the present invention to provide a signal processing circuit that prevents pseudo lock of the timing recovery PLL.